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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Novel Bumping and Underfill Technologies for 3D IC Integration

  • Sung, Ki-Jun (Convergence Components & Materials Research Laboratory, ETRI, Package Design Technology Team of SK Hynix Semiconductor) ;
  • Choi, Kwang-Seong (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Bae, Hyun-Cheol (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kwon, Yong-Hwan (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Eom, Yong-Sung (Convergence Components & Materials Research Laboratory, ETRI)
  • Received : 2012.02.06
  • Accepted : 2012.07.05
  • Published : 2012.10.31
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Abstract

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

Keywords

References

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