Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Instructions and Data Prefetch Mechanism using Displacement History Buffer

변위 히스토리 버퍼를 이용한 명령어 및 데이터 프리페치 기법

  • Jeong, Yong Su (Department of Electronic Engineering, Inha University) ;
  • Kim, JinHyuk (Department of Electronic Engineering, Inha University) ;
  • Cho, Tae Hwan (Department of Electronic Engineering, Inha University) ;
  • Choi, SangBang (Department of Electronic Engineering, Inha University)
  • Received : 2015.07.01
  • Accepted : 2015.09.24
  • Published : 2015.10.25
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Abstract

In this paper, we propose hardware prefetch mechanism with an efficient cache replacement policy by giving priority to the trigger block in which a spatial region and producing a spatial region by using the displacement field. It could be taken into account the sequence of the program since a history is based on the trigger block of history record, and it could be quickly prefetching the instructions or data address by adding a stored value to the trigger address and displacement field since a history is stored as a displacement value. Also, we proposed a method of replacing at random by the cache replacement policy from the low priority block when the cache area is full after giving priority to the trigger block. We analyzed using the memory simulator program gem5 and PARSEC benchmark to assess the performance of the hardware prefetcher. As a result, compared to the existing hardware prefecture to generate the spatial region using a bit vector, L1 data cache miss rate was reduced about 44.5% on average and an average of 26.1% of L1 instruction misses occur. In addition, IPC (Instruction Per Cycle) showed an improvement of about 23.7% on average.

본 논문에서는 변위 필드를 이용해 히스토리 레코드를 생성하는 방법과 히스토리 레코드의 기준이 되는 트리거 블록에 우선 순위를 부여하여 효율적인 캐시 교체를 가능하게 하는 하드웨어 프리페치 기법을 제안한다. 히스토리 레코드의 트리거 블록을 기준으로 히스토리를 생성하기 때문에 프로그램의 시퀀스를 고려할 수 있으며, 히스토리를 변위 값으로 저장하기 때문에 트리거 주소와 변위필드에 저장된 값을 더해 빠르게 명령어 또는 데이터 주소를 프리페치 할 수 있다. 또한, 트리거 블록에 우선순위를 부여하고 캐시 교체 정책으로 랜덤 교체 방법을 사용해 캐시 공간이 가득 찼을 때 우선순위가 낮은 블록부터 랜덤하게 교체하는 방법을 제안한다. 제안하는 하드웨어 프리페처의 성능을 평가하기 위해 메모리 분석 시뮬레이터인 gem5와 PARSEC 벤치마크 프로그램을 사용하였다. 그 결과 비트벡터를 이용해 공간영역을 생성하는 기존의 하드웨어 프리페처와 비교해 L1 데이터 캐시의 미스율은 평균 약 44.5% 감소하였고 L1 명령어 캐시의 미스율은 평균 약 31% 감소하였다. 또한 IPC (Instruction Per Cycle)는 평균 약 23.7% 향상을 보였다.

Keywords

References

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