Journal of Security Engineering (보안공학연구논문지)

Innovation in Secure and Intelligent Engineering Systems (보안공학연구지원센터)
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FPGA Implementation of ARIA Crypto-processor Based on Advanced Key Scheduling

개선된 키 스케쥴링 기반 ARIA 암호 프로세서의 FPGA 구현

  • Kang, Jae-Seok (Dept. of computer science and engineering, Anyang Univ.) ;
  • Kang, Min-Sup (Dept. of computer science and engineering, Anyang Univ.)
  • Received : 2016.09.15
  • Accepted : 2016.12.02
  • Published : 2016.12.31
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Abstract

In this paper, we present the implementation of ARIA crypto-processor based on advanced key scheduling. In the conventional approach of key setup process, both diffusion and substitution layers are commonly used repeatedly in each round function. However, In this proposed approach, an advanced key setup is introduced in such a way that two functions are merged into only one function, and it is shared for reducing hardware overhead. The proposed ARIA crypto-processor is coded in Veilog-HDL, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool. In order to verify the designed processor, timing simulation is also performed by using simulator, ModelSim 10.4a. Through the result of the logic synthesis, we showed that the number of Slices is about 1,550, and the system is operated with the maximum clock speed of 220.4MHz, where FPGA Xilinx XC5VSX50T is used as a target device.

본 논문에서는 FPGA 면적의 감소를 위한 개선된 키 스케쥴링 기반 ARIA 알고리듬의 FPGA 설계 및 구현에 관하여 기술한다. 기존의 ARIA 알고리듬은 키 초기화 과정에서는 확산 계층과 치환 계층의 사용을 반복하지만, 제안한 방법에서는 2 종류의 계층을 통합, 공유하도록 하여 하드웨어 오버헤드를 감소시킨다. 제안된 ARIA 알고리듬은 Verilog HDL을 이용하여 구조적 모델링을 행하였으며, Xilinx ISE 14.7 툴을 이용하여 논리 합성을 수행하였다. 실제 타이밍 검증은 Mentor Modelsim 10.4a 툴을 이용하여 타이밍 시뮬레이션을 수행하였다. Target Device을 XC5VSX50T로 하여 Slice는 총1,550개가 사용되었고, 최대 클럭 속도는 약 220.4Mhz로 동작함을 확인 하였다.

Keywords

References

  1. NSRI, Security and Performance Analysis of ARIA, http://www.nsri.re.kr/ARIA, (2003).
  2. Min-Sup Kang, Design of a High-speed FPGA-Based ARIA Cipher Processor, Journal of Security Engineering. (2014) Vol.11, No.3 , pp.195-206. https://doi.org/10.14257/jse.2014.06.01
  3. Younggap You, Seung-Youl Kim, Yong-Dae Kim, Jinsub Park, Low Power Cryptographic Design based on Circuit Size Reduction, Journal of the Korea Contents Association. (2007), Vol.11, No.2, pp.92-99.
  4. Jinsub Park, Yeonsang Yun, Young-Dae Kim, Sangwoon Yang, Taejoo Chang, Younggap You, Design and Implementation of ARIA Cryptic Algorithm, The Institute of Electronics Engineers of Korea - Semiconductor and Devices. (2005), Vol.42, No.4, pp.29-36.
  5. Hyun-Chang Yang, Kyung-Wook Shin, A Design of Compact and High-performance AES Processor Using Composite Field Based S-Box and Hardware Sharing, The Institute of Electronics Engineers of Korea - Semiconductor and Devices. (2008), Vol.45, No.8, pp.67-74.
  6. NSRI, ARIA Test Vectors, (2004).
  7. Dong-Hyeon Kim, Kyung-Wook Shin, An Efficient Hardware Implementation of ARIA Block Cipher Algorithm Supporting Four Modes of Operation and Three Master Key Lengths, Journal of the Korea Institute of Information and Communication Engineering. (2012), Vol.16, No.11, pp.177-184.
  8. Seong-Ju Ha, Chong-Ho Lee, Design of High Speed Encryption/Decryption Hardware for Block Cipher ARIA, The transactions of The Korean Institute of Electrical Engineers. (2008), Vol.57, No.9, pp.1652-1659.

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