Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Heterogeneous Device Packaging Technology for the Internet of Things Applications

IoT 적용을 위한 다종 소자 전자패키징 기술

  • Kim, Sarah Eunkyung (Graduate School of Nano-IT Design Convergence, Seoul National University of Science and Technology)
  • 김사라은경 (서울과학기술대학교 나노IT디자인융합대학원)
  • Received : 2016.08.26
  • Accepted : 2016.09.22
  • Published : 2016.09.30
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Abstract

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

IoT 적용을 위해서는 다종 소자를 높은 connectivity 밀도로 집적화시키는 전자패키징 기술이 매우 중요하다. FOWLP 기술은 입출력 밀도가 높고, 소자의 집적화가 우수하고, 디자인 유연성이 우수하여, 최근 개발이 집중되고 있는 기술이다. 웨이퍼나 패널 기반의 FOWLP 기술은 초미세 피치 RDL 공정 기술과 몰딩 기술 개발이 최적화 되어야 할 것이다. 3D stacking 기술 특히 웨이퍼 본딩 후 TSV를 제조하는 방법(via after bonding)은 가격을 낮추면서 connectivity를 높이는데 매우 효과적이라 하겠다. 하지만 저온 웨이퍼 본딩이나 TSV etch stop 공정과 같이 아직 해결해야할 단위 공정들이 있다. Substrate 기술은 두께를 줄이고 가격을 낮추는 공정 개발이 계속 주목되겠지만, 칩과 PCB와의 통합설계(co-design)가 더욱 중요하게 될 것이다.

Keywords

References

  1. Q. Zhang, "Overview of the Internet of Things(IoTs)", FYG5100 Lecture Note, HKUST (2013) from http://www.cs.ust.hk/-qianzh/FYTGS5100/fall2013/notes/Chapter1-IoT.pdf
  2. Internet of Things, Wikipedia from https://en.wikipedia.org/wiki/Internet_of_things
  3. W. Chen, "The challenges and opportunities of Advanced Packaging Materials", 12th ISMP-IAAC, Oct. 16 (2014).
  4. L. Srivastava, P. Biggs, T. Kelly, Y. Lozanova, L. P. Chavolla, J. Ponder, R. Sagalbayeva, S. Skvortsova and C. Sund, "Internet of Things", ITU Internet Report, (2005).
  5. D. Evans, "The Internet of Things, how the Next Evolution of the Internet Is Changing Everything", Cisco IBSG, April (2011) from https://www.cisco.com/c/dam/en_us/about/ac79/docs/innov/IoT_IBSG_0411FINAL.pdf
  6. C. Joo and H. Na, "A Study of Research Trend about Internet of Things", Information policy, 22(3), 3 (2015).
  7. I. Lee and K. Lee, "The Internet of Things (IoT): Applications, investments, and challenges for enterprises", Business Horizons, 58, 431 (2015). https://doi.org/10.1016/j.bushor.2015.03.008
  8. J. H. Lau, "Semiconductors and packaging for the Internet of Things", Chip Scale Review, May-June, 25 (2015).
  9. K. Suu, "High density packaging technology solution for smart ICT", IEEE Pan Pacific Microelectronics Symp., 1 (2016).
  10. M. Park, S. Kim and S. E. Kim, "TSV Liquid Cooling System for 3D Integrated Circuits", J. Microelectron. Packag. Soc., 20(3), 1 (2013). https://doi.org/10.6117/KMEPS.2013.20.3.001
  11. M. Park, S. Kim and S. E. Kim, "Study of chip-level liquid cooling for high-heat-flux devices", J. Microelectron. Packag. Soc., 22(2), 27 (2015). https://doi.org/10.6117/kmeps.2015.22.2.027
  12. Y. Jin, X. Baraton, S. W. Yoon, Y. Lin, P. C. Marimuthu, V. P. Ganesh, T. Meyer and A. Bahr, "Next Generation eWLB (embedded Wafer Level BGA) Packaging", IEEE 12th EPTC, 520 (2010).
  13. H. Hayashi, T. Takahashi, N. Shintani, T. Kondo, H. Marutani, Y. Takehara, K. Higaki, O. Yamagata, Y. Yamaji, A. Katsumata and Y. Hiruta, "A novel wafer-level fanout package ($WFOP^{TM}$) applicable to 50 ${\mu}m$ pad pitch interconnects", IEEE 13th EPTC, 730 (2010).
  14. C. Liu, S. Chen, F. Kuo, H. Chen, E. Yeh, C. Hsieh, L. Huang, M. Chiu, J. Yeh, T. Lin, T. Yeh, S. Hou, J. Hung, J. Lin, C. Jou, C. Wang, S. Jeng and D. Yu, "High-performance integrated fan-out wafer-level packaging (InFO-WLP): technology and system integration", IEEE IEDM, 14.1.1-14.1.4. (2012).
  15. T. Meyer, G. Ofner, S. Bradl, M. Brunnbauer and R. Hagen, "Embedded wafer level ball grid array (eWLB)", IEEE 10th EPTC, 994 (2008).
  16. J. Azemar and P. Garrou, "Fan-out packaging: what can explain such a great potential?", Chip Scale Review, May-June, 5 (2015).
  17. S. Kroehnert, L. Wang and L. Zhang, "Advancing fan-out wafer-level packaging for mobile applications", Chip Scale Review, Nov-Dec, 1 (2015).
  18. S. W. Yoon, B. Petrov and K. Liu, "Advanced wafer-level technology: enabling innovations in mobile, IoT and wearable electronics", Chip Scale Review, May-June, 54 (2015).
  19. J. Knickerbocker, C. S. Patel, P. S. Andry, C. K. Tsang, L. Paivikki Buchwalter, E. Sprogis, Hua Gan, R. R. Horton, R. Polastre, S. L. Wright, C. Schuster, C. Baks, F. Doany, J. Rosner and S. Cordes, "Three dimensional silicon integration using fine pitch interconnection,silicon processing and silicon carrier packaging technology", Proc. IEEE Custom Integrated Circuits Conf., 659 (2005).
  20. M. Koyanagi, "Heterogeneous 3D integration for internet of things", IEEE ICSITC, 1 (2014).
  21. J. Yannou and J. Baron, "3DIC and TSV Interconnects", Yole Development 2010 Report Series, (2010).
  22. S. E. Kim and S. Kim, "Wafer level Cu-Cu direct bonding for 3D integration", Microelectron. Eng., 137, 158 (2015). https://doi.org/10.1016/j.mee.2014.12.012
  23. Y. H. Cho, S. E. Kim and S. Kim, "Wafer Level Bonding Technology for 3D Stacked IC", J. Microelectron. Packag. Soc., 20(1), 7 (2013).
  24. S. Kang, J. Lee, E. Kim, N. Lim, S. Kim, S. Kim and S. E. Kim, "Fabrication and Challenges of Cu-to-Cu Wafer Bonding", J. Microelectron. Packag. Soc., 19(2), 29 (2012). https://doi.org/10.6117/kmeps.2012.19.2.029
  25. E. Kim and J. Sung, "Yield challenges in wafer stacking technology", Microelectron. Reliab., 48, 1102 (2008). https://doi.org/10.1016/j.microrel.2008.03.010
  26. S. E. Kim, "Manufacturing yield challenges for wafer-towafer integration", J. Microelectron. Packag. Soc., 20(1), 1 (2013). https://doi.org/10.6117/kmeps.2013.20.1.001
  27. M. J. Wolf, "3D Heterogeneous Integration as a Holistic Approach", 10th Int. Nanotech. Conf. Comm. Cooper. (2014).
  28. S. E. Kim, R. S. List and T. Letson, "Etch stop layer for silicon (si) via etch in three-dimensional (3-d) wafer-to-wafer vertical stack", US patent No. 6,645,832 (2003).
  29. Sony's Stacked CMOS Image Sensor Solves All Existing Problems in One Stroke (2012) from http://www.sony.net/Products/SC-HP/cx_news_archives/img/pdf/vol_68/sideview_vol68.pdf
  30. S. Sukegawa, T. Umebayashi, T. Nakajima, H. Kawanobe, K. Koseki, I. Hirota, T. Haruta, T. Haruta, M. Kasai, K. Fukumoto, T. Wakano, K. Inoue, H. Takahashi, T. Nagano, Y. Nitta, T. Hirayama and N. Fukushima, "A 1/4-inch 8M pixel back-illuminated stacked CMOS image sensor", Proc. IEEE ISSCC, 484 (2013).
  31. R. Beica, "The growth of advanced packaging: Technology overview, applications and market trends", SEMICON Taiwan, Sep. (2015).
  32. D. Hu, "The requirement of future substrate", iNEMI Sub. & Packag. Tech. Workshop (2014).
  33. A. Gerstenmayer, D. Drofenik and V. Lam, "Trends, Markets & Strategy Update", AT&S Analyst Day (2015) from http://www.ats.net/investors/downloadcentre/
  34. K. Lee, S. Cha and P. Shim, "Form factor and cost driven advanced package substrates for mobile and IoT applications", IEEE CSITC, 1 (2016).
  35. V. Sundaram, H. Chan, F. Liu, R. Tummala, H. Roberts, S. Lamprecht, K. Matejat, A. Oezkoek, S. Kennedy, J. Dobrick and D. Baars, "Super high density two metal layer ultra thin organic substrates for next generation system-on-package (SOP), SIP and ultra-fine pitch flip-chip packages", 14th Pan Pacific Microelectron. Symp., (2009).

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